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Test Code : HP0-M37
Test denomination : HP Data Protector Software Fumdamentals For UNIX
Vendor denomination : HP
real questions : 59 existent Questions

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HP Data Protector Software Fumdamentals For UNIX book

what's going to substitute DRAM and NAND, and When? | HP0-M37 existent Questions and VCE practice Test

long, lengthy in the past, again when Richard Nixon became president of the united states of the us, magnetic cores had been the predominant desktop memory technology. actually, magnetic cores were pretty much the only functional reminiscence know-how for two a long time. although they had hand-woven rope reminiscence for ROM, simplest the Apollo space computer systems and the HP 9100 computer calculator used it. My 1954 “Britannica booklet of the year”—a existent book, made from lifeless bushes—says that RCA Laboratories introduced a working core memory in 1953 that used a 100×100 grid of wires to wield 10,000 ferrite toroids.

Jay Forrester’s project Whirlwind team at MIT besides developed a magnetic core reminiscence that was first used within the groundbreaking, true-time Whirlwind computer around the very time as RCA’s announcement. Magnetic core reminiscence right away grew to become the reminiscence of alternative for mainframe computer systems (and eventually minicomputers), tipping mercury delay traces (derived from World warfare II radar know-how) and CRT-based mostly electrostatic reminiscences onto the first rate scrap pile of memory heritage.

Magnetic core reminiscence rapidly swept away these different two reminiscence applied sciences, mostly for 2 motives: magnetic core storage changed into fantastically speedy, however, just as vital, it become persistent. You may reduce the verve to a properly designed magnetic core memory and, for those who flipped the verve switch back on, barnone the saved bits would nevertheless subsist precisely the plot you left them in memory. within the mainframe and minicomputer period, magnetic core memory always functioned as each ROM and RAM.

Then, in 1970, Intel let the serpent into magnetic core’s garden of Eden via maxim the trade’s first DRAM, the 1103, which truly managed to toil just a Little reliably a 12 months later, after the chip’s fifth stepping. Intel had been situated in 1968 for the categorical direct of replacing magnetic core memory with semiconductor reminiscence. Magnetic core memory became hand-woven, usually via ladies with constant, petite hands, sharp eyesight, and buckets of patience. memory carriers not ever succeeded in automating the manufacturing manner for magnetic core planes.

Bob Noyce and Gordon Moore centered Intel to toss the nascent built-in circuit mass-production technology they’d developed at Fairchild at core memory’s velocity, means, and price obstacles. Intel’s 1103 DRAM turned into born ready to relish the Moore’s legislation rocket sled, and DRAM has now been King of recollections for almost half a century. regardless of not being persistent, DRAM is low-priced and it’s quick.

We use EEPROM for nonvolatile semiconductor storage, notably NAND glimmer EEPROM as a result of its cost per bit is comparatively low and since it’s persistent. however, storing information in NAND glimmer memory is besides exceedingly slow.

Jim Pappas, Intel’s Director of expertise Initiatives, emphasized NAND glimmer reminiscence’s velocity problem throughout his presentation titled “Why Persistent memory matters,” which he offered as a member of the “good Monsters—rising reminiscence technologies” panel at the synchronous Storage Visions 2018 conference held on the Hyatt Regency inn in Santa Clara, California.

And simply what's Persistent memory (PM)? The cynical acknowledge is that it’s the latest, au courant identify for storage-category memory—the memory that’s speculated to sit between DRAM and glimmer in terms of each velocity and price per bit. although, I wager we’ve become alert of being sort mindful and so this new class of memory apparently essential a new name.

A greater technical acknowledge is that PM is memory that’s pretty much as quick as RAM and tons quicker than NAND glimmer memory, however, love NAND Flash, it’s besides nonvolatile and much low-cost than DRAM on a per-bit basis.

here’s a chart introduced with the aid of Tom Coughlin and Jim handy at SNIA’s Storage Developer conference this yr. (SNIA is the storage Networking trade association.) The chart properly summarizes the reminiscence hierarchy slot (a brilliant blue circle) being targeted by using PM, plotted as bandwidth in megabytes per 2nd versus price per gigabyte on a log-log scale. observe that during this chart, the blue coterie is marked “3D XPoint” nonetheless it’s roughly the equal location being focused by means of barnone PM applied sciences.

figure 1: Persistent memory (PM) will occupy the rate/bandwidth hollow that sits between DRAM and NAND glimmer storage. PM occupies the blue circle, which indicates 3D XPoint as a placeholder for barnone PM candidate applied sciences. (Chart from Coughlin & handy PM presentation at SNIA SDC 2018.)

there are lots of candidate technologies for implementing PM including MRAM (magnetic RAM), ReRAM (resistive RAM) and CBRAM (conductive bridging RAM), FeRAM (ferroelectric RAM), and PCM (phase-trade reminiscence), just to identify just a few. To succeed, any candidate know-how making an attempt to worm its approach into the memory/storage hierarchy needs to provide more bandwidth than the applied sciences below it and should cost much less per bit (or gigabyte) than applied sciences above it on the chart.

there are many candidate reminiscence/storage applied sciences for a similar intent that there are such a lot of horses within the Kentucky Derby: considered one of them is bound to win. besides the fact that children the outcomes’s far less certain in the PM Derby, there’s a lot of money to subsist made if anyone of those applied sciences manages to ripen into a cheap, manufacturable technique.

In his Storage Visions presentation, Pappas first recounted that people fill a tough time mentally connecting desktop-scale time periods (microseconds and nanoseconds) to the human scale (seconds, minutes, hours, and days), so he used the photo in design 2 to deliver visceral distinction between the latencies of PM and storage.

determine 2: Slowing reminiscence speeds to human speeds underscores just how gradual storage instruments are. (photograph supply: Jim Pappas, SNIA, and Intel)

think about that DRAM latency is one 2d. (consistently, it’s on the order of tens of nanoseconds.) they barnone carry an inner, one-2d reference clock. It’s their heartbeat. Assuming that one second is the baseline time scale, then an SSD satisfies a erudition request in the time that it takes you to walk a mile. That’s a lot of heartbeats, ignoring the fill an result on this walk has on your coronary heart rate. the use of this very multiplied time scale, you fill sufficient time to trip a bicycle from Intel’s campus in Hillsboro, Oregon to Miami beach whereas looking ahead to a tough disk drive to fulfill a data request.

This basic analogy underscores latest storage know-how’s chief vulnerability: It’s tons, much too laggard compared to processor speeds. determine three provides a extra technical assessment of storage and PM memory latencies.

determine three: the load/store threshold at around 200 nsec differentiates reminiscence from storage. (photograph source: Jim Pappas, SNIA, and Intel)

notice that storage instruments (HDDs, SSDs, and NVMe glimmer reminiscence) barnone plunge into the red zone. That’s the gradual zone. That’s the zone that’s sooooo sluggish, the processor’s conveniently no longer going to hold around waiting to rep a response for a erudition request. In design 3’s crimson zone, it’s extra productive for the processor to switch context and originate a further job during the time the computing device’s storage subsystem should fulfill the storage request.

A hypothetical PM technology with an information latency of lower than a hundred nsec falls into the load/save region in design 1. in case you strengthen a fast, bulk-reminiscence know-how—a memory expertise that may reply with a latency of handiest a brace of hundred nanoseconds—then the processor is looking ahead to the information request to subsist fulfilled, as a result of context switches require two to three microseconds, which is plenty longer than the wait time and for this judgement tons less productive. the usage of context switching to masks storage latency effortlessly makes no relish when PM is present.

There might subsist nevertheless other causes for the usage of context switching, despite the fact, but the addition of PM to the reminiscence/storage hierarchy would appear to fill some wonderful and high-quality implications for multicore processor architectures as neatly. If the want for context switching diminishes on account of the presence of PM, then it seems to me that the use of extra processor cores to race simultaneous applications may neatly surge, to extra crop back the percentage of processor time wasted on context switches. It’s a probable future virtuous cycle for software structure.

in line with Pappas, PM’s additional velocity will in the discontinuance disrupt the basics of computing device design, but now not instantly. it is going to accomplish so in three evolutionary stages. SNIA calls these ranges “Horizons,” as shown in design 4.

determine four: SNIA says that PM will subsist adopted in three degrees. (graphic source: Jim Pappas, SNIA, and Intel)

The existing file device structure and hierarchy emerge on the left in design four. The application makes a request of the file device, knowing that the facts it seeks isn’t in leading reminiscence. The file materiel interprets the application’s information request into assorted calls to the utility disk driver, which effects in the eventual retrieval of the records from the storage hardware. The file device and disk driver are software gaskets, used to reconcile the hardware processor’s high velocity to the disk force’s gradual latency, which is glacially separated from the processor’s load/keep location.

For the final half century, functions don’t talk at once to storage systems; they originate requests in the course of the working device’s file system, which quite simply insulates the software operating on the processor from the mechanics of the storage hardware. This compartmentalization makes it feasible to replace the utility disk driver and the hardware storage materiel with PM middleware and PM hardware, as a first step within the evolution of PM-based desktop architecture.

note that we’re already seeing this delivery to happen. during this first evolutionary step, an utility accesses statistics stored in PM during the present file device. this first step replaces sluggish storage with quicker PM.

despite the fact Pappas became watchful not to overly choose one candidate PM expertise over an additional in his presentation, his organization, Intel, added and began transport Optane DC PM DIMMs again in August. (See “the new, New Intel Unleashes a expertise Barrage.”) These Optane DIMMs plug into DDR4 memory slots on an Intel Skylake motherboard and originate the Optane PM directly obtainable to the processor. (be aware: Optane PM DIMMs are not moreorless as speedy as DDR4 SDRAM DIMMs, so a compatible memory controller is besides required.)

notwithstanding the processor has direct access to the Optane reminiscence area, current applications are written to entry storage through the file gadget, which explains this primary evolutionary step. The functions must subsist rewritten to rob replete abilities of the Persistent reminiscence. (SNIA could subsist creating a “center of excellence” for PM applications next yr.)

That brings us to the column marked Horizon 2 in design 4. in the evolutionary stage that SNIA calls Horizon 2, the file materiel continues to subsist for backwards compatibility, however a PM API library has been added in order that new purposes can use API calls to directly tackle data stored in PM. Such accesses through these API calls may subsist some distance faster than having access to statistics during the file equipment, so the Horizon 2 evolutionary step offers a velocity potential over Horizon 1.

within the ultimate stage, known as Horizon 3 by artery of SNIA, the operating device without delay accommodates PM APIs, and compilers use them to directly entry information stored in PM attached to the processor bus. How soon will this happen? Linux, Microsoft windows, and VMWare fill barnone included PM APIs already, in accordance with Pappas. The newest Java virtual computer (JVM) has besides included built-in PM APIs, so any Java software can now entry PM as neatly.

SNIA should subsist protecting a PM peak on January 24, 2019 within the very Santa Clara Hyatt Regency inn that hosted Storage Visions 2018. The relish is free. PM peak underwriters consist of Intel, smart Modular technologies, AgigaTech, OpenFabrics Alliance, Netlist, and Viking expertise. in case you originate a decision to attend, subsist certain to thank them for getting you into SNIA’s PM peak for gratis.


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