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contemporary Consulting-Specifying Engineer webcast presenters Tom Divine, PE, project supervisor, Smith Seckman Reid Inc., and Kenneth Kutsmeda, PE, LEED AP, Jacobs Engineering, reply reader questions on what unusual code necessities will suggest for consulting engineers.
Q: When is it required to contain a 3 pole and four pole ATS?
Q: With recognize to breaker coordination; what are the favorite electronic trips: LI, LS/I, LSI, or LSIG?
Q: finish you advocate dual hot-standby manage PLCs when installing parallel gensets?
Q: Are schools regarded to exist stage 1 or degree 2 amenities? usually, stage 1 is needed for fitness trust or mission censorious facilities handiest.
Q: what's the intent/aim of corporeal isolating the well-known department and lifestyles defense branches? Can one contain a risky repercussion on the different?
Q: Is mineral-insulated (MI) cable obligatory for not obligatory standby generator feeder circuits?
Q: Does the ten-2nd vigour restoration start time apply to the main service or to the conclusion employ gadget?
Q: Does the emergency device consist of conductors and different device upstream from an ATS on the regular aspect of the ATS?
Q: should the emergency provider switchboard that feeds the ATSs exist in a sever elbowroom from the elbowroom that contains the ATSs?
Q: If the only vital concern is egress lights, can that exist addressed with battery lights, and if so, can my system exist standby best?
Q: When referring to the NEC as regarding the EPSS, finish you deserve to additionally correspond with article 695 elevators and 517 hospitals for further requirements?
Q: How lengthy does the crank examine should exist accomplished on the generator?
Q: Is the employ of closed transition transfer switches informed for smooth 1 facilities? Any concerns with the usage of closed transition switches?
Q: What are the requirements for the life security and significant fork programs when the constructing—specifically a talented nursing facility—has a replete structure backup generator? finish you still require sever ATSs, besides the fact that they contain sever panels and wiring within the constructing? Contractors account here's now not essential.
Q: If I even contain a device per Article 701 and Article 702 software, what branches finish the battery charger, gasoline pump, and dampers accumulate connected to?
Q: If a sanatorium is to exist 100% backed up with the aid of turbines, is it a violation of NEC 517.30(B)(4)-switch Switches to accumulate rid of outright switch switches by using providing Medium Voltage generators and tie them thru a paralleling outfit to a Medium Voltage Distribution Switchgear at the significant Utility Plant? switch of vigour may exist at the Medium Voltage switchgear.
Q: might the 517.34 outfit exist considered as a 701 device?
Q: To verify under on-website or transportable load monetary institution, finish amenities contain a checking out switch change to connect the weight monetary institution to the gadget and supply that auto removal of load monetary institution if utility energy fails privilege through load monetary institution testing?
Q: are you able to combine Article seven hundred-class masses and Article 701-classification loads in the equal switchgear and on the identical OCPD of a generator?
Q: whereas performing the two hour load verify per 7.13.four.3, I assume the generator OEM manufacturing facility can discharge only a 2 hour reactive load verify at rated power factor to correspond to 7.13.4.three.2, relevant?
– Edited by using Jessica DuBois-Maahs, affiliate content supervisor, CFE Media, jdmaahs(a)cfemedia.com.
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swiftly migrating highbrow property (IP) from one foundry to yet another and from one technique node to the next will furthermore exist a difficult, however indispensable, a section of the business, mainly if the IP is generated and delivered as hardmacro IP. That’s as a result of tough IP or a GDSII netlist versus soft IP, RTL or gate-stage netlist ought to exist accessible for outright primary foundries and for a large selection of technique nodes at each foundry.
Designing unusual recollection IP is essentially a manual assignment that includes greater analog circuits —cost pumps, voltage regulators and tang amplifiers, for example — than most common sense designs. At four megabytes (Mb), the design tribulation dealing with the layout supervisor and his implementation crew is bold.
These considerations are gardenvariety of reminiscence design, and the Kilopass team ran into them when designing a simultaneous 4-Mb reminiscence IP block. Its tang offers techniques through which other groups can overcome these challenges.
To ease the burden, the group recognized facets of the design that could exist automated, liberating them to pay attention to essential analog elements that ought to exist tailor-made for someone foundry and technique. The outcome is an electronic design automation (EDA) device trek developed for the newest anti-fuse non-unstable reminiscence (NVM) product line.
Exploiting the EDA device circulation
the employ of commercially purchasable EDA solutions, the primary stint to exist automated was speedy and accurate entry of design concepts, together with managing design intent in a fashion that flowed naturally in the schematic. This allowed designers to visualize and buy into account the numerous interdependencies of an analog or mixed-signal design and its results on circuit performance.
In designing this 4-Mb memory, about 10 percent of the design required the layout team to import a GDSII netlist developed by using an additional inside team. The project of merging the current layout with the comfort of the recollection design became a simple fashion requiring a day of manual vicinity and route or connecting I/Os and routing verve and floor.
The crew made employ of the potential to embed design constraints within the netlist handed between the entrance-end design team and the implementation team. Up unless that point, those constraints had been communicated by using cryptic notes on the schematic. as an example: Specify that two gates obligatory to exist matched or a particular internet is censorious and its optimum size requisite to no longer exist passed within the layout. Communicated the ancient manner, when the schematic become given to the implementation engineer, the designer could simplest hope that the implementation crew achieved the favored effect.
The implementation crew built a brand unusual recollection with the aid of making a separate recollection mobile then replicated it to build the more complicated arrays — a bottom-up approach versus the generic right-down approach that tremendous digital SoC design groups compose employ of. The reminiscence consisted of partially cell comprising two transistors.
once the bit mobilephone was created and optimized, the telephone became replicated along a horizontal line of size n (32, for instance), as distinct in the schematic. once the line of reminiscence cells became created, it turned into replicated vertically m number of rows (32, as an example), as targeted in the schematic. during this method, the implementation engineer created a 1-Mb reminiscence array. The system was repeated three more instances to create the 4-Mb memory, a two-via-two matrix of 1-Mb arrays.
In setting up the introductory netlist, the front-end dressmaker labeled each of the bit cells and its linked vigor, ground, bit line and note line. He then precise the number of bit cells to exist powered by course of a given energy internet to compose unavoidable that each phone obtained the equal quantity of present.
The capacity to set constraints in the netlist passed to the implementation engineer ensured the design intent became captured in closing layout.
Automating Repetitive sheperd projects
Automating repetitive projects tremendously decreased the time to complete the layout as neatly. for example, labeling the bit line, notice line, feel amplifier, and energy and ground for a 4-Mb reminiscence can buy appreciable time if done manually. Surrendering the assignment to the EDA device reduced the chore to a handful of keyboard operations.
In a pull-down menu, the implementation engineer achieved a profile that asked for the signal identify, variety of pins to exist labeled, x and y coordinates of the first signal, spacing between pins, and the measurement of the text. From this counsel, the design device created each particular person signal name.
once the reminiscence IP become applied for the 40-nanometer (nm) technique at foundry A, the layout crew turned into confronted with converting the reminiscence to 40 nm at one other foundry. With the automated EDA stream, this was decreased to a two-step procedure: layer mapping followed by statistics manipulation. in the first step, the mapping table for foundry A’s forty-nm library become changed with the mapping desk for foundry B’s 40-nm library. The appliance then immediately produced a layout for foundry B. The fashion became not absolutely automatic, as every foundry has its own exciting rules; hence exceptions that don't map one-to-one are highlighted.
The implementation engineer examined outright generated exceptions then made fundamental alterations. as an instance, in foundry A, the bit phone might furthermore employ layer C and D, whereas in foundry B, layer D and E are used. once the conversion changed into accomplished, a design rule examine (DRC) become performed along with remaining verification.
This automation took half the time compared with ranging from scratch, enabling rapid migration of IP from one foundry to an additional. while designing unusual recollection IP, such as Kilopass’ Gusto anti-fuse NVM, continues to exist more often than not a sheperd effort, facets may furthermore exist automated, enabling the layout and implementation group to concentrate on censorious analog features that must exist tailor-made for a person foundry and process.
creator Bio: Bernd Stamme is Director for advertising and functions at Kilopass know-how. He has more than 15 years of tang within the IP and semiconductor industry. prior to Kilopass, he become the Director of IP know-how at SiRF technology managing the licensing and a success integration of third-celebration IP into SiRF’s GPS chip units. earlier than SiRF, he held administration positions in LSI logic’s CoreWare organization and worked on high-pace SerDes IP, communication interfaces and processor core. Stamme holds a Dipl.-Ing. degree in Electrical Engineering from FH Bielefeld in Germany.
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Rapidly migrating intellectual property (IP) from one foundry to another and from one process node to the next can exist a challenging, but necessary, section of the business, especially if the IP is generated and delivered as hardmacro IP. That’s because hard IP or a GDSII netlist versus soft IP, RTL or gate-level netlist must exist available for outright major foundries and for a wide selection of process nodes at each foundry.
Designing unusual recollection IP is largely a manual stint that involves more analog circuits —charge pumps, voltage regulators and sense amplifiers, for example — than most logic designs. At four megabytes (Mb), the design tribulation facing the layout manager and his implementation team is formidable.
These issues are typical of recollection design, and the Kilopass team ran into them when designing a recent 4-Mb recollection IP block. Its tang offers ways in which other teams can overcome these challenges.
To ease the burden, the team identified elements of the design that could exist automated, freeing them to concentrate on censorious analog elements that must exist tailored for an individual foundry and process. The result is an electronic design automation (EDA) appliance stream developed for the latest anti-fuse non-volatile recollection (NVM) product line.
Exploiting the EDA appliance Flow
Using commercially available EDA solutions, the first stint to exist automated was rapid and accurate entry of design concepts, including managing design intent in a course that flowed naturally in the schematic. This allowed designers to visualize and understand the many interdependencies of an analog or mixed-signal design and its effects on circuit performance.
In designing this 4-Mb memory, about 10 percent of the design required the layout team to import a GDSII netlist developed by another internal team. The stint of merging the existing layout with the comfort of the recollection design was a simple process requiring a day of manual region and route or connecting I/Os and routing power and ground.
The team made employ of the skill to embed design constraints in the netlist passed between the front-end design team and the implementation team. Up until that point, those constraints were communicated by cryptic notes on the schematic. For example: Specify that two gates needed to exist matched or a specific net is censorious and its maximum length must not exist exceeded in the layout. Communicated the obsolete way, when the schematic was given to the implementation engineer, the designer could only hope that the implementation team achieved the desired result.
The implementation team built a unusual recollection by creating a separate recollection cell then replicated it to build the more complex arrays — a bottom-up approach versus the conventional top-down approach that large digital SoC design teams employ. The recollection consisted of a bit cell comprising two transistors.
Once the bit cell was created and optimized, the cell was replicated along a horizontal line of length n (32, for example), as specified in the schematic. Once the line of recollection cells was created, it was replicated vertically m number of rows (32, for example), as specified in the schematic. In this manner, the implementation engineer created a 1-Mb recollection array. The process was repeated three more times to create the 4-Mb memory, a two-by-two matrix of 1-Mb arrays.
In developing the initial netlist, the front-end designer labeled each of the bit cells and its associated power, ground, bit line and word line. He then specified the number of bit cells to exist powered by a given power net to ensure that each cell received the same amount of current.
The skill to set constraints in the netlist passed to the implementation engineer ensured the design intent was captured in final layout.
Automating Repetitive Manual Tasks
Automating repetitive tasks greatly reduced the time to complete the layout as well. For example, labeling the bit line, word line, sense amplifier, and power and ground for a 4-Mb recollection can buy considerable time if done manually. Surrendering the stint to the EDA appliance reduced the chore to a handful of keyboard operations.
In a pull-down menu, the implementation engineer completed a profile that asked for the signal name, number of pins to exist labeled, x and y coordinates of the first signal, spacing between pins, and the size of the text. From this information, the design appliance created each individual signal name.
Once the recollection IP was implemented for the 40-nanometer (nm) process at foundry A, the layout team was confronted with converting the recollection to 40 nm at another foundry. With the automated EDA flow, this was reduced to a two-step process: layer mapping followed by data manipulation. In the first step, the mapping table for foundry A’s 40-nm library was replaced with the mapping table for foundry B’s 40-nm library. The appliance then automatically produced a layout for foundry B. The process was not completely automated, as each foundry has its own unique rules; thus exceptions that finish not map one-to-one are highlighted.
The implementation engineer examined outright generated exceptions then made necessary adjustments. For example, in foundry A, the bit cell may employ layer C and D, whereas in foundry B, layer D and E are used. Once the conversion was completed, a design rule check (DRC) was performed along with final verification.
This automation took half the time compared with starting from scratch, enabling rapid migration of IP from one foundry to another. While designing unusual recollection IP, such as Kilopass’ Gusto anti-fuse NVM, continues to exist mostly a manual effort, elements can exist automated, enabling the layout and implementation team to concentrate on censorious analog elements that must exist tailored for an individual foundry and process.
Author Bio: Bernd Stamme is Director for Marketing and Applications at Kilopass Technology. He has more than 15 years of tang in the IP and semiconductor industry. Prior to Kilopass, he was the Director of IP Technology at SiRF Technology managing the licensing and successful integration of third-party IP into SiRF’s GPS chip sets. Before SiRF, he held management positions in LSI Logic’s CoreWare organization and worked on high-speed SerDes IP, communication interfaces and processor core. Stamme holds a Dipl.-Ing. Degree in Electrical Engineering from FH Bielefeld in Germany.
One of the hardest choices encoding technicians contain to compose is deciding between hardware and software. Hardware-based encoders and transcoders contain had a performance handicap over software since computers were invented. That's because dedicated, limited-purpose processors are designed to rush a specific algorithm, while the general-purpose processor that runs encoding software is designed to ply several functions. It's the specialist versus the jack-of-all-trades.
In the past few years, processors and workflows contain changed. The considerable disruptor has been time and the economics of Moore's Law, which famously says that the number of transistors incorporated in a chip will approximately double every 24 months. The ratiocinative outcome of Moore's law is that the CPUs accumulate more powerful by a factor of two every few years, but more recently processing power seems to double every few months. Lately, Intel -- whose co-founder Gordon Moore coined Moore's Law -- has been adding specialty functions along with its math co-processors to equalize the differences between general-use processors and specialty processors.
There are many layers and elements to both a general-purpose processor and a task-specific hardware processor. The general-purpose CPU is the most common -- there are literally billions of them in outright manner of computing devices -- while the more purpose-oriented processors comprehend digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and integrated circuits (ICs) that are available for various industrial appliances and widely used in cellphones. Many of the structures and elements are similar across outright types, but there are considerable differences. If you are not intimate with the elements of the various types, here are the basic structures of both.The General-Purpose CPU
The general-purpose CPU is laid out with elastic core elements as the arithmetic logic unit (ALU), control unit (CU), and accessory elements that proffer extra features for performance. Basically these two cores talk to each other, bring in recollection as needed, and route travail to the other elements. Other elements comprehend I/O processors, logic gates, integrated circuits, and -- on most newer processors and especially on the Intel Xeon processors -- a beefy math co-processor. The math co-processor assists the ALU and can ply the more extreme and complex mathematical computations. Essentially, it gives the processor the extra horsepower it might require.The Dedicated Processor
Specific-purpose hardware encoders contain been around longer than general-purpose processors, and the latter contain been slower at mathematical equations or algorithm problems. History is vitally well-known to understand the market and technology, not to mention accumulate a sense of what the future holds. The earliest example of encoding was in 1965, when the Intelsat 1 (Early Bird) became the first commercial deployment of a satellite to downlink video and audio. Since then, the world has been using specific processors to process video, and the technology has made leaps and bounds to proffer higher density and quality.
This is a generic layout of a video ARM DSP. The ARM core runs the embedded operating system, working fancy a traffic cop to control input and output.
Dedicated processors -- such as dedicated signal processors (DSPs), graphics processing units (GPUs), and vector processors -- outright contain a very similar design structure. A basic and most common factor is an I/O manager, which has a tiny onboard operating system along with memory. This is the traffic cop, controlling input and output. Then there are multiple specialized processing modules that execute the desired instructions very quickly and that DSPs and other dedicated processors support. Unlike a general-purpose processor, which has many practicable generic instructions that may not exist most efficient for the stint at hand, dedicated processors dependence on accelerated, per-function instructions that are more job-specific.
Dedicated processors and encoders contain a variety of applications and workflows. If you sight at the major users of professional encoders, you will espy that in many cases they dependence on specialized encoders. The following well-known companies compose DSP chips: LSI Corp.; Texas Instruments, Inc.; Analog Devices, Inc.; Sony; and Magnum Semiconductor. These DSPs are used in devices such as media gateways, telepresence devices, cellphones, and military and radar processing.
FPGAs are now very well-liked implementations of DSP functions because of their flexibility of setup and upgrade. Since they are field-upgradeable, their development costs for the user are significantly cheaper than DSPs and application-specific integrated circuits (ASICs; more on those in a moment) from the traditional DSP providers. You can espy FGPAs from Altera Corp. and Xilinx, Inc. that contain DSP functions built in. If you want a board or system that is easier to upgrade in the field, then this is probably the best course to go.
While each manufacturer will tweak its design slightly, this is an overview of how communications and packets stream into the modules of DSPs and ASICs.
Another implementation of the dedicated processor is the ASIC. These factory-programmed DSPs are used everywhere cost is a crucial consideration, because they proffer special functionality at optimal cost and performance. In general, they are more expensive to design but are cost-effective for any appliance or board manufacturer to implement into their systems. Many manufacturers of DSPs furthermore manufacture ASICs; companies such as NXP Semiconductors, Broadcom Corp., and Freescale, Inc. furthermore compose custom ASIC DSPs.
If you ever open up a hardware encoding appliance -- from IP media gateways to broadcast encoder and decoders -- you will espy several of the chips previously listed. You can find appliances for every industry. Today you will find a dedicated hardware-based encoding device from Harmonic, Inc.; Harris; Tandberg Data; or NTT Communications in every TV station or cable TV headend, and you'll find appliances or cards from ViewCast Corp. or Digital Rapids in many hybrid encoding farms, since they accelerate some of the functions in the hardware. If you've watched a video on YouTube, then you contain seen video encoded by RGB Networks with the RipCode equipment, which used massive numbers of Texas Instruments, Inc. DSPs.Pros and Cons of Hardware Encoders
There are always some pros and cons when it comes to specific design hardware encoders and dedicated appliances. The dedicated hardware approach with DSPs or chips is the faultless solution for media gateways and in low latency military applications. They are designed to rush 24/7 with dinky or no human interaction. There are some processors that can encode an entire frame in the 1ms-10ms (millisecond) sweep and FPGAs that can encode in the 10ms-30ms range. These processes allow for the creation of appliances where the encoding latency is less than 100ms from encode to transmission to decode. privilege now you can only accumulate low latency using the privilege DSPs, ASICs, and FPGAs. The medium lifespan of an appliance is 5-10 years depending on the configuration and manufacturer. Similar lifetimes are assumed for systems that rarely change, such as satellite uplink or cable system encoders.
The primary drawback of dedicated hardware-based encoding is that the codec on the processor is generally impossible to upgrade. Every DSP, ASIC, or FPGA is based on an algorithm that was finalized years ago. By the time the chip is ready to exist sold, the codec is 6 months to a year old. Add more design cycles for the appliance development and manufacturing, and the nearby result is a device based on a codec that's a year or more old. If improvement to the codec comes out, the chip or device might never exist able to integrate the unusual codec or technology due to the manufacturer or the course the chip was designed. The dedicated DSP approach can deliver a lot of money, but at the expense of flexibility. Those chips finish just what they were originally designed to finish and nothing more.
Video comes into a hardware encoder to a media gateway, which will compose adjustments to the video stream to address network conditions and the nearby user’s video decoding device. When done, it will route these modifications to the video decoder.
There's another issue with dedicated chip-based encoders: Who determines the quality of the codes and streams? Is it a DSP engineer, a compressionist, or the producer and director? In a TV station, it's usually a combination of chief engineer and executive producer who resolve what station image goes over the air. If they employ a hardware encoder, in many cases decisions about encoding parameters contain been taken out of their hands. The broadcast engineer has to travail within the parameters the chip manufacturer has allowed nearby users to change, signification that while there is usually some control, there may not exist as much as a producer or engineer would like. There are only so many operations and cycles you can achieve on a chip, so some functionality is uneconomical to implement.The Pros and Cons of Software Encoders
General-purpose CPUs participate some similarities and architecture with dedicated processors. They are designed to ply the everyday functions of your PC or server, and they are optimized to finish mundane tasks such as word processing. This is why your motherboard has a powerful graphics card in your machine; it's a specialty function that is best offloaded to a specific-designed processor. If you finish any nonlinear video editing, you likely contain a capture card with some specialty processors to give you real-time output or transitions.
In the encoding and streaming industry, they mostly employ a capture board and one or more of many available software encoding packages. There are algorithms and formulas for every application, from live encoding to file-based transcoding to software-based decoding. These days most software-based encoders contain hooks in the code to offload unavoidable elements to accelerate or allow multiple CPUs to rush parallel functions to accumulate the best performance and quality. More recently, Intel is offering some onboard GPUs that feature decoding with MPEG, analysis of a video stream's motion vectors, and other functions.
This overview shows how a GPU or video accelerator is laid out. Again, one device works as a traffic cop to route travail to the usurp processors, then takes the video streams back and reassembles them together, allowing video to exist encoded at a faster rate.
Software encoders contain allowed users to exist much more elastic in responding to the needs of specific customers or events, and they outright employ the same general-purpose processors and capture boards to champion more video formats and standards. This has been an handicap for software encoders for a long time. They are light to reconfigure and use.
The software encoding industry has recently seen battles between open source and closed source. There are some notable pioneering closed source companies that helped drive the development of software encoding and streaming: Microsoft; real Networks, Inc.; Sorenson Communications; and Adobe Systems, Inc. laid out the framework for modern streaming and web-based video. They contain been around since the beginning, and in many cases they financed the codecs that became standards.
In addition to these pioneering companies, there has been a recent movement to open source. Some of the earlier versions such as x264 and the open source library in the University of California-Berkeley provide the foundation for most software encoders. Code is added every so often and allows others to program their custom apps. The better-known ones such as VideoLan (VLC), FFmpeg, and WebM are creating unusual versions and are catching on in generic use. Some are even getting funding from some of the larger public companies. The most notable example is WebM, which is being funded mostly by Google, which made the VP8 codec open source after it acquired On2 Technologies. outright this competition and activity is creating better products for consumers. The tremendous companies realize open source development and innovation is faster-moving than their own, allowing the market to grow more quickly than it otherwise might.
But software-based encoding has some drawbacks. The most well-known parameters of encoding are quality, flexibility, price, latency, and support.
Software encoding's greatest advantages over absolute hardware encoders are its flexibility and quality. Software has always been able to adopt and update incredibly fast. When unusual codec optimizations reach out, encoding package updates follow very soon after.
Software encoding can enable the producer, engineer, or other user to accumulate precisely the quality and image that they want, unlike the automated hardware solution, where the user has no utter in what the overall image is and outcome will be. Some larger encoding firms hire color consultants and compressionists, along with programmers and delivery experts, outright of whom assist the executive producers and directors determine what the overall outcome should sight like. It's a broadcast approach for streaming.
Later this year or in early 2013, Intel will release its Xeon Phi sequence of massive parallel coprocessors, which will travail with existing Xeon processors and workflows.
So if software encoding wins in flexibility and quality, what about hurry or latency? While some highly tuned hardware encoders proffer a latency down in the 30ms range, most software solutions rush in the 300ms-500ms range, if not higher. Most people who employ software encoding realize they are sacrificing some hurry for quality. outright that matters is whether or not they can accumulate the resolution and framerate they want; if it's delayed some, the workflow can exist designed to accommodate it. On the other hand, if you require the lowest latency and fastest delivery, you will contain to give up some quality.
Cost of champion is of course an well-known issue. Will the proprietary company sustain making the version you're using, or is there a haphazard it will exist withdrawn from the market? How much will the updates and upgrades cost? It turns out that upgrades in the open source community are relatively frequent, whereas upgrades in propriety software are less so.
While some people assume that open source products proffer lower quality or reliability than proprietary software, that's not necessarily the case. FFmpeg, VLC, and WebM are outright significantly upping their quality. On the other hand, proprietary software packages such as Sorenson and MainConcept contain furthermore stood the test of time and continue to find widespread use. Interestingly, MainConcept and Sorenson are two of the few companies whose solutions are used in both software and hardware encoding; both provide codecs for the PC environment as well as specifically designed chips.Changes in Media Consumption, Changes in Media Encoding
General-purpose hardware-based decoders are now playing an well-known role in the overall media viewer world, especially as more and more viewers are quitting cable and going the IP route for outright of their video consumption. Roku, Boxee, and other IP set-top boxes are DSP-based decoders. At the same time, more and more consumers are adopting Android or iOS devices and using them as personal media players, and each device brings with it its own set of ideal encoding profiles and parameters. You'll find you requisite to finish custom scaling and probably want to proffer the highest practicable complexity. Then again, you requisite to disburse more CPU cycles per frame, which will require more encoding time but create a better outcome.Conclusion
There will always exist a battle between hardware encoding and software encoding. Who will win in various market segments? Why a hardware encoder versus the software encoder? Even now they are starting to espy more specialty functionality appended on the general-purpose CPUs, due to the miniaturization and density of transistors and processors. For instance, Intel recently agreed to buy 190 patents and 170 patent applications from RealNetworks, and for years the company has been adding graphics processing and other accelerators or processing engines.
Dedicated hardware encoding wins in unique parallel processing situations when massive amounts of data requisite to exist processed, as well as in low latency communications such as real-time monetary and some military applications. It furthermore leads in situations where you want to just install the encoding appliance and let it finish its thing, such as in situations with YouTube that can dependence on automated, predefined resolutions and bitrates for a massive amount of viewers. But software encoders will exist the appliance of selection in most applications. It's faster and cheaper to encode with software than in hardware, and once you espy how the market responds to your output, it's faster and cheaper to compose modifications.
So, finish you most value flexibility and lower costs? Then software is probably your best bet. finish you requisite low latency and stream density or automated auto-transcoding for the mobile market? Then a hardware solution probably is best for you.
This article appears in the October/November, 2012, issue of Streaming Media magazine under the title "The Specialist Vs. the Jack-of-All-Trades."
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